Name
Abstract | ||
|---|---|---|
Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-mum technology. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2003003 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
tsmc 0.18-mum technology,previous low-complexity technique,image processing application,important technique,microprocessor chips,edge-oriented image scaling processor,interpolation,edge-oriented area-pixel,pipeline architecture,image resolution,edge-oriented image,edge-oriented area-pixel scaling processor,better image quality,computational complexity,image edge,feature extraction,vlsi implementation,vlsi,edge detection,edge catching technique,image scaling,area-pixel scaling technique,image edge features,low-complexity vlsi architecture,processing rate,circuits,image quality,pixel,image processing,very large scale integration | Computer science,Edge detection,Image processing,Image quality,Feature extraction,Electronic engineering,Pixel,Very-large-scale integration,Image resolution,Image scaling | Journal |
Volume | Issue | ISSN |
17 | 9 | 1063-8210 |
Citations | PageRank | References |
15 | 0.86 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Yin Chen | 1 | 314 | 38.47 |
| Chih-Yuan Lien | 2 | 91 | 9.64 |
| Chi-Pin Lu | 3 | 15 | 0.86 |