Paper Info
Title
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Abstract
To enable fast and accurate evaluation of HW/SW implementationchoices of on-chip communication, we presenta method to automatically generate timed OS simulationmodels. The method generates the OS simulation modelswith the simulation environment as a virtual processor.Since the generated OS simulation models use finalOS code, the presented method can mitigate the OS codeequivalence problem. The generated model also simulatesdifferent types of processor exceptions. This approach providestwo orders of magnitude higher simulation speedupcompared to the simulation using instruction set simulatorsfor SW simulation.
Year
DOI
Venue
2002
10.1109/DATE.2002.998365
DATE
Keywords
Field
DocType
automatic generation,os simulation model,sw implementationchoices,soc design,processor exception,operating systems,simulation environment,presenta method,os simulationmodels,simulatorsfor sw simulation,magnitude higher simulation,virtual processor,fast timed simulation models,os codeequivalence problem,logic simulation,integrated circuit design,network on a chip,switches,communication networks,design optimization,simulation model,network synthesis,virtual machines,drams,packet switching,application specific integrated circuits,chip,instruction sets,operating system
Virtual machine,Computer science,Instruction set,Parallel computing,Application-specific integrated circuit,Real-time computing,Simulation modeling,Integrated circuit design,Logic simulation,Virtual Processor,Operating system,Speedup
Conference
ISBN
Citations 
PageRank 
0-7695-1471-5
41
3.64
References 
Authors
13
4
Name
Order
Citations
PageRank
Sungjoo Yoo1696.90
Gabriela Nicolescu2718.03
Lovic Gauthier315117.13
Ahmed A.Jerraya41031123.45