Name
Abstract | ||
|---|---|---|
The automation of custom hardware design often focuses on hardware optimizations for smaller portions of code that dominate the design execution. The same presumption can be stated for custom processor design. The data path of the processor can be well optimized for particular blocks of code that are formed during control flow extraction. However, larger source codes can have tens of blocks that result from Control Flow Graph (CFG). We implemented a global semi-automated flow that hierarchically forms the set of blocks which contributions are modeled into processor architecture. Resulting processor model is translated to RTL description and implemented inside FPGA logic. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/EUROCON.2013.6625209 | 2013 IEEE EUROCON |
Keywords | Field | DocType |
Custom Processor Design, No-Instruction-Set Computer, High-Level Synthesis, Data Path Design, FPGA Implementation | Control flow graph,Source code,Computer science,Parallel computing,High-level synthesis,Control flow,Field-programmable gate array,Electronic engineering,Automation,Processor design,Computer hardware,Microarchitecture | Conference |
Citations | PageRank | References |
2 | 0.39 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Danko Ivosevic | 1 | 4 | 1.46 |
| Vlado Sruk | 2 | 26 | 6.73 |