Title
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
Abstract
Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. Experience with the use of static timing-analysis methods and the tools based on them in the automotive and the aeronautics industries is positive. However, both the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. In fact, the architecture determines whether a static timing analysis is practically feasible at all and whether the most precise obtainable results are precise enough. Results contained in this paper also show that measurement-based methods still used in industry are not useful for quite commonly used complex processors. This dependence on the architectural development is of growing concern to the developers of timing-analysis tools and their customers, the developers in industry. The problem reaches a new level of severity with the advent of multicore architectures in the embedded domain. This paper describes the architectural influence on static timing analysis and gives recommendations as to profitable and unacceptable architectural features.
Year
DOI
Venue
2009
10.1109/TCAD.2009.2013287
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
future architecture,time-critical embedded system,precise enough,analysis method,architectural development,memory hierarchy,aeronautics industry,unacceptable architectural feature,precise obtainable result,architectural influence,static timing-analysis method,timing constraint,static timing analysis
Journal
28
Issue
ISSN
Citations 
7
0278-0070
112
PageRank 
References 
Authors
4.02
26
6
Search Limit
100112
Name
Order
Citations
PageRank
Reinhard Wilhelm13640434.27
Daniel Grund241218.24
Jan Reineke354327.61
Marc Schlickling41447.27
Markus Pister517110.84
Christian Ferdinand61124.02