Name
Abstract | ||
|---|---|---|
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Self-timed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations in a 180nm CMOS process comparing the Distributed Clock Generator presented in this paper and an H-tree clock distribution system, each clocking a 16mm 脳 16mm area suggests a 30% power savings. Also worst case skew was reduced from 27ps to 2ps while using a clock period equivalent to 9 FO4 gates. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASYNC.2005.29 | ASYNC |
Keywords | DocType | ISSN |
cmos process,clock generator,global clocking,fo4 gate,worst case skew,power saving,clock period equivalent,digital system,clock tree,h-tree clock distribution system,self-timed circuitry,clock signal | Conference | 1522-8681 |
ISBN | Citations | PageRank |
0-7695-2305-6 | 10 | 0.84 |
References | Authors | |
6 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Scott Fairbanks | 1 | 189 | 15.13 |
| Simon Moore | 2 | 38 | 3.74 |