Name
Abstract | ||
|---|---|---|
In this paper we address the important problem of instruction fetch for future wide issue superscalar processors. Our approach focuses on understanding the interaction between software and hardware techniques targeting an increase in the instruction fetch bandwidth. That is the objective, for instance, of the Hardware Trace Cache (HTC). We design a profile based code reordering technique which targets a maximization of the sequentiality of instructions, while still trying to minimize instruction cache misses. We call our software approach, Software Trace Cache (STC). We evaluate our software approach, and then compare it with the HTC and the combination of both techniques. Our results on PostgreSQL show that for large codes with few loops and deterministic execution sequences the STC offers better results than a HTC. Also, both the software and hardware approaches combine well to obtain improved results. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1023/A:1019992713965 | International Journal of Parallel Programming |
Keywords | Field | DocType |
hardware trace cache,hardware approach,deterministic execution,commercial applications,software trace cache.,software trace cache,code reordering technique,code layout,better result,postgresql show,instruction fetch,hardware technique,software approach,instruction cache | Pipeline burst cache,Computer architecture,Cache invalidation,Cache,Computer science,Parallel computing,Cache algorithms,Bandwidth (signal processing),Software,Smart Cache,Maximization | Journal |
Volume | Issue | ISSN |
30 | 5 | 1573-7640 |
Citations | PageRank | References |
2 | 0.37 | 20 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alex Ramirez | 1 | 934 | 62.01 |
| Josep-Ll. Larriba-Pey | 2 | 16 | 2.38 |
| Carlos Navarro | 3 | 2 | 0.37 |
| Mateo Valero | 4 | 4520 | 355.94 |
| Josep Torrellas | 5 | 3838 | 262.89 |