Name
Abstract | ||
|---|---|---|
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.5121/vlsic.2010.1303 | Clinical Orthopaedics and Related Research |
Keywords | Field | DocType |
energy efficient,quantum computer,optical computing,input output | Adder,Subtractor,Computer science,Efficient energy use,Quantum computer,CMOS,Electronic engineering,Serial binary adder,Carry-save adder,Optical computing | Journal |
Volume | ISSN | Citations |
abs/1009.6 | International Journal of VLSI Design & Communication Systems,
1.3(2010),pp-23-34 | 6 |
PageRank | References | Authors |
0.68 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. G. Rangaraju | 1 | 8 | 1.09 |
| U. Venugopal | 2 | 6 | 0.68 |
| K. N. Muralidhara | 3 | 8 | 1.09 |
| K. B. Raja | 4 | 34 | 9.60 |