Title
Low-power fanout optimization using multiple threshold voltage inverters
Abstract
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, power, and input capacitance, the fanout tree is converted to a set of inverter chains and for each chain the optimal sizes and threshold voltages are determined. Experimental results show that using this technique, the power dissipation of fanout tree is reduced by an average of 33% for a state-of-the-art CMOS technology.
Year
DOI
Venue
2005
10.1145/1077603.1077628
international symposium on low power electronics and design
Keywords
DocType
ISBN
power dissipation,threshold voltage,multiple threshold voltage inverters,introducing splitting,low-power fanout optimization,inverter chain,input capacitance,fanout tree,optimal size
Conference
1-59593-137-6
Citations 
PageRank 
References 
3
0.41
7
Authors
3
Name
Order
Citations
PageRank
Behnam Amelifard1817.38
Farzan Fallah255743.73
Massoud Pedram378011211.32