Name
Abstract | ||
|---|---|---|
Quality of hardware implementation is an important factor in selecting the NIST SHA-3 competition finalists. As a third-round candidate algorithm of SHA-3, BLAKE algorithm achieved excellent performance in software implementation. In order to adapt to the resource-limited and high-speed system, this paper carried out a [4G] hardware architecture based on BLAKE-32 algorithm. To complete the calculation, our architecture divides each round cycle into two cycles and each cycle executes 4G functions. Therefore, by adopting this architecture, the resources consuming can be reduced and a higher working frequency can be achieved. After validating the Verilog implementation of our architecture on a FPGA platform, the simulating results show that our [4G]-BLAKE structure has several advantages as a 26.8% area reducing, an up to 112 MHz acceleration in maximum working frequency and an up to 2048 Mbit/s enhancement in maximum throughput rate. © 2012 IEEE. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/BMEI.2012.6512910 | BMEI |
Keywords | Field | DocType |
hardware implementation,fpga,hash function,blake-32,sha-3,cryptography,field programmable gate arrays,resource allocation,hardware description languages | Throughput (business),Computer science,SHA-3,Field-programmable gate array,NIST,Resource allocation,Verilog,Computer hardware,Hardware description language,Hardware architecture | Conference |
Volume | Issue | ISSN |
null | null | null |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zheng-lin Liu | 1 | 74 | 12.07 |
| Xin Dong | 2 | 0 | 0.34 |
| Yizhi Zhao | 3 | 0 | 0.68 |
| Dongfang Li | 4 | 106 | 15.34 |