Name
Title | ||
|---|---|---|
Column-parallel continuous-time ΣΔ ADC with implicit front-end variable gain amplifier |
Abstract | ||
|---|---|---|
This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit pre-amplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/MWSCAS.2013.6674633 | Circuits and Systems |
Keywords | Field | DocType |
sigma-delta modulation,cmos image sensors,amplifiers,2nd order resistor capacitor-based loop filter,analog-to-digital converters,voltage 1.4 v,column-parallel readout circuit,pre-amplification function,word length 2 bit,size 0.18 mum,continuous time systems,digital filters,front-end variable gain amplifier,column-parallel continuous-time σδ adc,frequency 50 mhz,digital integrator based decimination filter,cmos image sensor,column-parallel continuous-time sigma delta adc | Variable-gain amplifier,Digital filter,Capacitor,Computer science,Delta-sigma modulation,Electronic engineering,Chip,Control engineering,Resistor,Clock rate,Amplifier | Conference |
Volume | Issue | ISSN |
null | null | 1548-3746 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fang Tang | 1 | 0 | 0.34 |
| Yuan Cao | 2 | 0 | 0.34 |
| Xiaojin Zhao | 3 | 4 | 5.48 |