Name
Title | ||
|---|---|---|
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology |
Abstract | ||
|---|---|---|
Very-Large-Scale Integration (VLSI) is the process of establishing integrated circuits. Although the process is getting more and more complex, the development of VLSI has effectively increased the design capability and system performance. Power dissipation for large and complex circuits has always been a concern for engineers on the leading edge of technology. This paper aims at establishing a new standard cell library. Moreover, the most relevant definitions, classifications and details (including power and performance optimization) of the new standard cell library are presented in this paper. ©2011 IEEE. |
Year | DOI | Venue |
|---|---|---|
2011 | null | ISOCC |
Keywords | DocType | Volume |
IC design,Layout,LVS,Standard cell library | Conference | null |
Issue | ISSN | Citations |
null | null | 0 |
PageRank | References | Authors |
0.34 | 4 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun Zhao | 1 | 27 | 7.67 |
| W. Pan | 2 | 0 | 0.34 |
| Cezhou Zhao | 3 | 0 | 0.34 |
| K. L. Man | 4 | 0 | 0.34 |
| Joongho Choi | 5 | 0 | 0.34 |
| J. Chang | 6 | 1 | 2.05 |