Name
Abstract | ||
|---|---|---|
This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fractional time difference with a cascading chain of 2×time amplifiers. A digitally self-calibrated TA circuit is developed to achieve large input range and stable gain. Simulation results show that implemented in SMIC 0.13μm CMOS, the proposed TDC can achieve a minimum resolution of 0.8ps, a measurement range of 14bits, and a power dissipation of 2mW at 60MHz. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASICON.2011.6157277 | ASICON |
Keywords | Field | DocType |
cmos integrated circuits,smic,size 0.13 micron,all-digital pll,minimum-resolution subexponent tdc,fractional time difference,power dissipation,digital phase locked loops,time-to-digital converter,time amplifier,frequency 60 mhz,adpll,time-digital conversion,measurement range,time resolution,cmos,power 2 mw,integrated circuits,time frequency analysis,integrated circuit,noise,time to digital converter,frequency synthesizer | Exponent,Computer science,Dissipation,CMOS,Electronic engineering,Time–frequency analysis,Time difference,Integrated circuit,Time-to-digital converter,Electrical engineering,Amplifier | Conference |
Volume | Issue | ISSN |
null | null | 2162-7541 E-ISBN : 978-1-61284-191-5 |
ISBN | Citations | PageRank |
978-1-61284-191-5 | 0 | 0.34 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaolu Liu | 1 | 1 | 1.07 |
| Yan Na | 2 | 12 | 9.20 |
| Xi Tan | 3 | 73 | 14.27 |
| Min Hao | 4 | 11 | 4.81 |