Title
Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13μm CMOS
Abstract
A high-performance 25%-duty-cycle divider in 0.13μm CMOS for multi-mode wireless communication applications is presented. Compared with the conventional designs, this work features reduced power consumption and low phase noise by adopting the divide-by-2 divider with intrinsic 25%-duty-cycle outputs. The performance of this work has been demonstrated in a WCDMA/GSM multi-mode multi-band receiver implemented in 0.13μm CMOS. © 2011 IEEE.
Year
DOI
Venue
2011
10.1109/ASICON.2011.6157275
ASICON
Keywords
Field
DocType
phase noise,cmos integrated circuits,wireless communication,integrated circuit design,duty cycle,gsm,switches,spread spectrum communication,low power electronics
GSM,Frequency divider,Computer science,Duty cycle,Phase noise,Electronic engineering,CMOS,Integrated circuit design,Electrical engineering,Wilkinson power divider,Low-power electronics
Conference
Volume
Issue
ISSN
null
null
2162755X
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Song Hu1505.44
Weinan Li2114.24
Yumei Huang300.68
Zhiliang Hong45214.17