Name
Abstract | ||
|---|---|---|
The correlation network of neurons emerges as an important mathematical framework for a spectrum of applications including neural modeling, brain disease prediction and brain-machine interface. However, construction of correlation network is computationally expensive, especially when the number of neurons is large and this prohibits real-time applications. This paper proposes a hardware architecture using hierarchical systolic arrays to reconstruct the correlation network. Through mapping an efficient algorithm for cross-correlation onto a massively parallel structure, the hardware can accomplish the network construction with extremely small delay. The proposed structure is evaluated using Field Programmable Gate Array (FPGA). Results show that our method is three orders of magnitudes faster than the software approach using desktop computer. This new method enables real-time network construction and leads to future novel devices of real-time neuronal network monitoring and rehabilitation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/IEMBS.2011.6091702 | 2011 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC) |
Keywords | Field | DocType |
brain machine interface,hardware architecture,field programmable gate array,cross correlation,neurophysiology,real time,field programmable gate arrays,neuronal network,correlation,hardware,systolic array,spectrum,real time systems | Neurophysiology,Computer science,Massively parallel,Field-programmable gate array,Electronic engineering,Software,Network construction,Biological neural network,Hardware architecture | Conference |
Volume | Issue | ISSN |
2011 | null | 1557-170X |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bo Yu | 1 | 10 | 2.26 |
| Terrence Mak | 2 | 21 | 3.88 |
| Yihe Sun | 3 | 125 | 14.73 |
| Chi-Sang Poon | 4 | 54 | 10.88 |