Name
Abstract | ||
|---|---|---|
This paper presents a block-layered decoder architecture and efficient design techniques for quasi-cyclic nonbinary low-density parity-check (QC-NB-LDPC) codes. Based on a Min-Max decoding algorithm, an efficient block-layered decoder architecture for QC-NB-LDPC codes is proposed for fast decoder convergence. Further, a novel two-way merging Min-Max algorithm, which significantly reduces decoding latency, is proposed for check node processing. The NB-LDPC decoder using the proposed algorithm can provide a considerably higher throughput rate than that using a conventional Min-Max algorithm. The proposed (225, 165) NB-LDPC decoder over GF(24) is synthesized using a 90-nm CMOS process. It can operate at a clock rate of 400 MHz and achieve a data processing rate of 24.6 Mbps under 10 decoding iterations. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/s11265-013-0816-5 | Journal of Signal Processing Systems |
Keywords | Field | DocType |
Nonbinary,Low-density parity-check (LDPC) codes,Min-Max decoding,Two-way merging,Block-layered,VLSI | Throughput (business),Sequential decoding,Low-density parity-check code,Computer science,Parallel computing,Real-time computing,Viterbi decoder,Soft-decision decoder,Decoding methods,Very-large-scale integration,Clock rate | Journal |
Volume | Issue | ISSN |
78 | 2 | 1939-8018 |
Citations | PageRank | References |
2 | 0.38 | 20 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Changseok Choi | 1 | 33 | 7.39 |
| Hanho Lee | 2 | 205 | 40.92 |