Title
Verifying Relative Error Bounds Using Symbolic Simulation.
Abstract
In this paper we consider the problem of formally verifying hardware that is specified to compute reciprocal, reciprocal square root, and power-of-two functions on floating point numbers to within a given relative error. Such specifications differ from the common case in which any given input is specified to have exactly one correct output. Our approach is based on symbolic simulation with binary decision diagrams, and involves two distinct steps. First, we prove a lemma that reduces the relative error specification to several inequalities that involve reasoning about natural numbers only. The most complex of these inequalities asserts that the product of several naturals is less-than/greater-than another natural. Second, we invoke one of several customized algorithms that decides the inequality, without performing the expensive symbolic multiplications directly. We demonstrate the effectiveness of our approach on a next-generation Intel® processor design and report encouraging time and space metrics for these proofs.
Year
DOI
Venue
2014
10.1007/978-3-319-08867-9_18
CAV
Field
DocType
Volume
Single-precision floating-point format,Symbolic simulation,Reciprocal,Natural number,Floating point,Computer science,Binary decision diagram,Algorithm,Theoretical computer science,Square root,Lemma (mathematics)
Conference
8559
ISSN
Citations 
PageRank 
0302-9743
2
0.38
References 
Authors
16
2
Name
Order
Citations
PageRank
Jesse D. Bingham1101.22
Joe Leslie-Hurd221.05