Paper Info
Title
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
Abstract
The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
Year
DOI
Venue
2015
10.1109/TCSI.2014.2342380
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
microcontrollers,cmos process,psrr,integrated circuit testing,si,transistor circuits,power saving,resistance-locked loop (rll),power supply rejection,digital low dropout (dldo) regulator,resistance-locked loop,dldo regulator,cmos digital integrated circuits,size 40 nm,embedded digital low dropout regulator,voltage 0.6 v,dldo stability,current efficiency,voltage regulators,silicon,silicon area,duty compensator,peak current efficiency,elemental semiconductors,power integrated circuits,core device,stability,digital control,switches,noise,modulation
Duty cycle,Control theory,Electronic engineering,CMOS,Power supply rejection ratio,Transistor,MOSFET,Voltage regulator,Mathematics,Low-dropout regulator,Dropout voltage
Journal
Volume
Issue
ISSN
62
1
1549-8328
Citations 
PageRank 
References 
5
0.44
9
Authors
7
Name
Order
Citations
PageRank
Chaochang Chiu120721.42
Po-Hsien Huang250.44
Moris Lin351.11
Ke-Horng Chen437990.04
Ying-Hsi Lin511230.84
Tsung-Yen Tsai63720.41
Chao-Cheng Lee78618.59