Name
Title | ||
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18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS |
Abstract | ||
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In this work, the authors demonstrate an MMSE-NBLDPC iterative detector-decoder for a 4×4 256-QAM MIMO system to achieve an excellent error rate that improves with iterations, as shown in Fig. 18.7.1. To minimize latency over the iterative loop and improve throughput, the MMSE detector is divided into 4 task-based coarse pipeline stages so that all stages can operate in parallel. Both the number of stages and the stage latency of the detector are minimized, and the long critical paths are interleaved and placed in a slow clock domain to support a high data rate in a cost-effective way. The resulting MMSE detector achieves an 82% higher throughput compared, and almost 3.5× the throughput of the latest SD detector. The NBLDPC decoder is implemented using 78 processing nodes to enable fully parallel message passing. Serial Galois field (GF) processing is pipelined using a data forwarding technique to cut the decoding latency by 30% over the latest design. The detector and decoder exchange symbol log-likelihood ratios (LLR) that are efficiently computed based on the L1 distance to the nearest neighbors in the QAM constellation. To lower the power consumption, automatic clock gating is applied to stage boundary and buffer registers to save 53% of the detector power and 61% of the decoder power. The results are demonstrated in a 65nm MMSE-NBLDPC iterative detector-decoder test chip that achieves 1.38Gb/s detection and 1.02Gb/s decoding (5 iterations), consuming 26.5mW and 103mW, respectively. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISSCC.2015.7063064 | ISSCC |
Keywords | DocType | Citations |
mmse detector,automatic clock gating,serial galois field,CMOS integrated circuits,parallel message passing,mmse-nbldpc iterative detector-decoder,power consumption,bit rate 1.38 gbit/s,power 26.5 mW,data forwarding,size 65 nm,bit rate 1.02 gbit/s,nbldpc decoder,qam constellation,NBLDPC decoder,mimo communication,power 103 mw,telecommunication power management,QAM MIMO system,power 103 mW,QAM constellation,ldpc iterative detector decoder,cmos integrated circuits,least mean squares methods,MMSE nonbinary detector decoder,MIMO communication,bit rate 1.38 Gbit/s,LDPC iterative detector decoder,power 26.5 mw,quadrature amplitude modulation,CMOS integrated circuit,galois fields,Galois fields,qam mimo system,cmos integrated circuit,power 130 mW,MMSE detector,iterative decoding,bit rate 1.02 Gbit/s,serial Galois field,parity check codes,log-likelihood ratios,MMSE-NBLDPC iterative detector-decoder,mmse nonbinary detector decoder,power 130 mw | Conference | 1 |
PageRank | References | Authors |
0.41 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-Hsiang Chen | 1 | 16 | 4.68 |
| Wei Tang | 2 | 12 | 1.37 |
| Zhengya Zhang | 3 | 502 | 48.41 |