Name
Abstract | ||
|---|---|---|
This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCSII.2014.2368974 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
median filters,one-dimensional (1-d),signal transition,power consumption,low-power,median filter,low-power electronics,one-dimensional,one-dimensional median filter,low-power architecture,word-level two-stage pipelined filter,machine cycle,token ring,very large scale integration,one dimensional,logic gates,registers,computer architecture,pipelines,low power electronics | Logic gate,Pipeline transport,Median filter,Token ring,Electronic engineering,Very-large-scale integration,Power Architecture,Mathematics,Instruction cycle,Power consumption | Journal |
Volume | Issue | ISSN |
62 | 3 | 1549-7747 |
Citations | PageRank | References |
2 | 0.52 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ren-Der Chen | 1 | 6 | 1.72 |
| Pei-Yin Chen | 2 | 314 | 38.47 |
| Chun-Hsien Yeh | 3 | 30 | 5.85 |