Name
Abstract | ||
|---|---|---|
In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offers many advantages, such as nonvolatility, high performance, the small form factor, and low-power consumption, while achieving high chip integration with a specialized architecture for bulk data access. A unit of NFM's read and program operations, the page, has continuously grown. Although increasing page size reduces costs, it adversely affects performance because of the resultant side effects, such as fragmentation and wasted space, caused by the incongruity of data and page sizes. To address this issue, we propose a multiple-page-size NFM architecture and its management. Our method dramatically improves write performance through adopting multiple page sizes without requiring additional area overhead or manufacturing processes. Based on the experimental results, the proposed NFM improves write latency and NFM lifetime by up to 65% and 62%, respectively, compared with the single-page-size NFM. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2409055 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
multiple page sizes,nand flash memory (nfm).,decoding,very large scale integration,computer architecture | Small form factor,Computer science,Latency (engineering),Chip,Real-time computing,NAND gate,Page,Decoding methods,Computer hardware,Very-large-scale integration,Data access | Journal |
Volume | Issue | ISSN |
PP | 99 | 1063-8210 |
Citations | PageRank | References |
2 | 0.37 | 3 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jin Young Kim | 1 | 497 | 81.76 |
| Sang-Hoon Park | 2 | 2 | 0.37 |
| hyeokjun seo | 3 | 2 | 0.71 |
| Ki-Whan Song | 4 | 58 | 9.66 |
| Sungroh Yoon | 5 | 566 | 78.80 |
| Eui-Young Chung | 6 | 635 | 71.51 |