Name
Title | ||
|---|---|---|
Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics |
Abstract | ||
|---|---|---|
An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor's characteristics. This paper presents a model-fitting framework to predict the average read/write metrics of the SRAM cells in a lithography shot using only the measured transistor characteristics. The proposed framework is validated through the measurement result of 4750 samples of a 128-bit SRAM-array test structure implemented in a United Microelectronics Corporation 28-nm process technology. The experimental results show that the learned models can achieve at least 97.77% R-square on fitting the shot-level read static noise margin, write margin, and read current based on 2375-sample testing data. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2418998 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
array test-structure,sram characterization,model-fitting,process monitor,test-time reduction.,radio frequency,time measurement,transistors | Microelectronics,Computer science,Static random-access memory,Real-time computing,Radio frequency,Electronic engineering,Lithography,Test data,Transistor,Test structure,Electrical engineering,Write margin | Journal |
Volume | Issue | ISSN |
PP | 99 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shu-Yung Bin | 1 | 0 | 0.34 |
| Shih-Feng Lin | 2 | 0 | 0.34 |
| Ya Ching Cheng | 3 | 0 | 0.34 |
| Wen-Rong Liau | 4 | 0 | 0.68 |
| alex hou | 5 | 0 | 0.34 |
| Mango Chia-Tso Chao | 6 | 52 | 9.86 |