Name
Title | ||
|---|---|---|
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS |
Abstract | ||
|---|---|---|
As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISSCC.2015.7062922 | Solid- State Circuits Conference - |
Keywords | DocType | Citations |
CMOS integrated circuits,adaptive equalisers,decision feedback equalisers,error statistics,integrated circuit interconnections,phase locked loops,signal conditioning circuits,BER,CMOS integrated circuit,DFE,adaptive pattern match,backplane architecture,backplane interconnects,channel length,chip-to-chip backplane,data rate adjustment PLL,decision feedback equalizer,error statistics,multirate links,multistandard backplane signal conditioner,pattern matched adaptive equalizer,serial links,size 28 nm | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. KAWAMOTO | 1 | 13 | 3.70 |
| Norimatsu, T. | 2 | 9 | 2.22 |
| Kogo, K. | 3 | 3 | 0.86 |
| Yuki, F. | 4 | 0 | 0.68 |