Paper Info
Title
A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS
Abstract
A Binary Frequency Shift Keying transmitter particularly suited for the recently introduced USB Power Delivery standard is presented here. The proposed architecture uses a combination of intelligent frequency planning, an unmodulated high frequency PLL, a digital clock rate converter, and a sine-weighted DAC impedance matched to the power-line network. This combination simultaneously achieves frequency keying and output signal generation in a novel highly integrated way. It achieves a Figure of Merit and a data-rate-normalized energy efficiency better than or comparable to generic Direct Digital Synthesis architectures and previously published FSK designs, at a fraction of their die area. Details of its architecture and implementation, 180 nm BiCMOS measurement results, and comparison with best existing designs are presented.
Year
DOI
Venue
2015
10.1109/VLSID.2015.89
VLSI Design
Keywords
Field
DocType
bicmos integrated circuits,carrier transmission on power lines,digital-analogue conversion,frequency shift keying,impedance matching,phase locked loops,radio transmitters,signal generators,bicmos measurement,usb power delivery standard,usb power line communication,binary frequency shift keying transmitter,bit rate 300 kbit/s,digital clock rate converter,direct digital synthesis,frequency 23.2 khz,intelligent frequency planning,power line network,signal generation,sine-weighted dac,size 180 nm,unmodulated high frequency pll,frequency shift keying transmitters,driver circuit,power amplifier,power line communication
Computer science,Frequency-shift keying,Amplitude and phase-shift keying,Keying,Frequency offset,Minimum-shift keying,Electronic engineering,On-off keying,Direct digital synthesizer,Electrical engineering,USB
Conference
ISSN
Citations 
PageRank 
1063-9667
0
0.34
References 
Authors
6
2
Name
Order
Citations
PageRank
Aswin Srinivasa Rao100.34
Karthik Subburaj241.84