Name
Abstract | ||
|---|---|---|
In recent times, the usage of Domino logic in design of high performance circuits is increasing. In addition to its high performance advantage, the Domino logic style also offers flexibility in designing individual cells. Flexible height and width of cells gives the designer an advantage to realize a large variety of functions. This gives a scope for library free mapping. In this work, we present an approach for mapping a Domino logic circuit using on-the-fly technique. First, we present a node mapping algorithm which maps a given Domino logic net list using on-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the critical path of the circuit for delay and area improvement. Finally, we find an optimum re-ordering set which can obtain maximum delay and area savings. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed mapping approach called Delay Area Aware Mapping (DAAM) obtained 21% improvement in area and 17% improvement in delay compared to the existing work. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSID.2015.83 | VLSI Design |
Keywords | Field | DocType |
logic circuits,logic design,daam,delay area aware mapping,domino logic circuit,equivalence table,library free mapping,node mapping algorithm,on-the-fly mapping technique,domino logic,cell re-ordering,logic effort,on-the-fly mapping | Domino logic,Logic gate,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Electronic engineering,Real-time computing,Logic level,Logic family,Asynchronous circuit | Conference |
ISSN | Citations | PageRank |
1063-9667 | 0 | 0.34 |
References | Authors | |
7 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sai Praveen Kadiyala | 1 | 2 | 2.82 |
| Debasis Samanta | 2 | 227 | 37.98 |