Paper Info
Title
Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications
Abstract
Efficient cryptographic architectures are used extensively in sensitive smart infrastructures. Among these architectures are those based on stream ciphers for protection against eavesdropping, especially when these smart and sensitive applications provide life-saving or vital mechanisms. Nevertheless, natural defects call for protection through design for fault detection and reliability. In this paper, we present implications of fault detection cryptographic architectures (Pomaranch in the hardware profile of European Network of Excellence for Cryptology) for smart infrastructures. In addition, we present low-power architectures for its nine-to-seven uneven substitution box [tower field architectures in GF(3³)]. Through error simulations, we assess resiliency against false-alarms which might not be tolerated in sensitive intelligent infrastructures as one of our contributions. We further benchmark the feasibility of the proposed approaches through application-specific integrated circuit realizations. Based on the reliability objectives, the proposed architectures are a step-forward toward reaching the desired objective metrics suitable for intelligent, emerging, and sensitive applications.
Year
DOI
Venue
2015
10.1109/TVLSI.2014.2382715
VLSI) Systems, IEEE Transactions  
Keywords
Field
DocType
application-specific integrated circuit (asic),reliability,smart infrastructures.,computer architecture,fault detection,hardware
General protection fault,False alarm,Eavesdropping,Computer science,Fault detection and isolation,Cryptography,Real-time computing,Electronic engineering,Error detection and correction,Stream cipher,Integrated circuit,Embedded system
Journal
Volume
Issue
ISSN
PP
99
1063-8210
Citations 
PageRank 
References 
14
0.58
15
Authors
3
Name
Order
Citations
PageRank
Mehran Mozaffari Kermani1221.76
Reza Azarderakhsh238945.65
Anita Aghaie3243.17