Name
Title | ||
|---|---|---|
A 2 mW, 50 dB DR, 10 MHz BW 5 Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF |
Abstract | ||
|---|---|---|
A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (ΔΣ) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm2 chip is fabricated in a 0.18 μm CMOS process. Measurements show that the prototype five-path TI BP ΔΣ modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCSI.2014.2347234 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
CMOS integrated circuits,band-pass filters,delta-sigma modulation,feedforward,invertors,operational amplifiers,radio receivers,ADC,CMOS process,auxiliary inverters,bandpass delta-sigma modulator,bandwidth 10 MHz,digital-IF receiver,feed-forward topology,frequency 50 MHz,inverter-based OTA,power 2 mW,power-efficient time-interleaved architecture,prototype five-path TI BP ΔΣ modulator,recursive loop,size 0.18 mum,Bandpass $DeltaSigma$ modulator,inverter-based OTA,low power,low voltage,radio receiver,switched-capacitor circuit,time-interleaved ADC | Inverter,Band-pass filter,Delta-sigma modulation,Chip,Cmos process,Electronic engineering,Modulation,Bandwidth (signal processing),Low voltage,Mathematics | Journal |
Volume | Issue | ISSN |
62 | 1 | 1549-8328 |
Citations | PageRank | References |
1 | 0.35 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Inhee Lee | 1 | 275 | 33.89 |
| Gunhee Han | 2 | 313 | 42.20 |
| Youngcheol Chae | 3 | 349 | 53.43 |