Steamroller Module and Adaptive Clocking System in 28 nm CMOS - Citegraph

Paper Info

Title
Steamroller Module and Adaptive Clocking System in 28 nm CMOS

Abstract
This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. The Steamroller module occupies 29.47 mm 2 and contains 236 million transistors. Various aspects of the core design are covered including the power and timing methodologies as well as design challenges moving from 32 nm SOI to 28 nm Bulk CMOS. Adaptive clocking, one of the key features used for core power efficiency, is described in detail.

Year	DOI	Venue
2015	10.1109/JSSC.2014.2357428	Solid-State Circuits, IEEE Journal of
Keywords	DocType	Volume
CMOS digital integrated circuits,clocks,high-k dielectric thin films,system-on-chip,AMD Kaveri APU SoC,AMD Steamroller module,adaptive clocking system,core power efficiency,high-k metal gate bulk CMOS process,power methodology,size 32 nm to 28 nm,timing methodology,28 nm CMOS,flip-flops,high-frequency CMOS design,microprocessors,power efficiency	Journal	50
Issue	ISSN	Citations
1	0018-9200	8
PageRank	References	Authors
0.80	0	16

Authors (16 rows)

Cited by (8 rows)

References (0 rows)

Name	Order	Citations	PageRank
Kathryn Wilcox	1	8	0.80
Robert Cole	2	63	164.40
Fair, H.R.	3	8	0.80
Kevin Gillespie	4	13	2.29
Harry R. Fair III	5	8	0.80
Aaron Grenat	6	41	5.21
Carson Henrion	7	17	2.98
Ravi Jotwani	8	8	0.80
Stephen Kosonocky	9	75	11.71
Benjamin Munger	10	8	0.80
Samuel Naffziger	11	136	16.42
Robert S. Orefice	12	8	0.80
Sanjay Pant	13	8	0.80
Donald A. Priore	14	13	2.29
Ravinder Rachala	15	8	0.80
Jonathan White	16	44	6.49

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