Name
Title | ||
|---|---|---|
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement |
Abstract | ||
|---|---|---|
For security-critical applications, the security and trust of devices must be tested before shipping. In this paper, we promote the use of On-Chip Power noise Measurements (OCM), in order to test security using side-channel techniques. We then propose for the first time a standard side-channel measurement setup using OCM. Finally, we provide some key ideas on methodology to integrate the validation of hardware security and trust in the standard testing flow, exploiting OCM. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASPDAC.2015.7059100 | Design Automation Conference |
Keywords | Field | DocType |
integrated circuit testing,noise measurement,system-on-chip,ocm,hardware security,on-chip power noise measurement,security-critical applications,shipping,side channel measurement setup,side channel techniques,test security | Hardware security module,Computer science,Electronic engineering,Power noise,Embedded system | Conference |
ISSN | Citations | PageRank |
2153-6961 | 1 | 0.36 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Fujimoto | 1 | 25 | 6.52 |
| Makoto Nagata | 2 | 285 | 76.47 |
| Shivam Bhasin | 3 | 311 | 58.38 |
| J-L. Danger | 4 | 125 | 9.83 |