Paper Info
Title
Hybrid DPWM implementation using coarse and fine programmable ADLL.
Abstract
In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8kHz and clock generator frequency of 90.3MHz allows us to attain SNR of 120dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.
Year
DOI
Venue
2014
10.1016/j.mejo.2014.04.038
Microelectronics Journal
Keywords
Field
DocType
Class-D digital audio amplifier,Digital Pulse Width Modulator (DPWM),Tapped delay line,Analog Delay Locked Loop (ADLL),Digital to time converter (DTC)
Clock generator,Baseband,Total harmonic distortion,Capacitor,Computer science,Schmitt trigger,Digital delay line,Electronic engineering,Modulation,Computer hardware,Design for manufacturability
Journal
Volume
Issue
ISSN
45
9
0026-2692
Citations 
PageRank 
References 
1
0.43
5
Authors
4
Name
Order
Citations
PageRank
Jacek Jasielski111.11
S. Kuta272.18
Witold Machowski382.87
Wojciech Kolodziejski471.85