Name
Abstract | ||
|---|---|---|
The increased transistor count resulting from ever-decreasing feature sizes has enabled the design of architectures containing many small but efficient processing units (cores). At the same time, many new applications have evolved with varying performance requirements. The fixed architecture of multiCore platforms often fails to accommodate the inherent diverse requirements of different applications. We present a dynamically reconfigurable multiCore architecture that detects program phase change at runtime and adapts to the changing program behavior by reconfiguring itself. We introduce simple but efficient performance counters to monitor vital parameters of reconfigurable architectures. We also present static, dynamic and adaptive reconfiguration techniques for reconfiguring the architecture. Our evaluation of the proposed reconfigurable architecture using an adaptive reconfiguration technique shows an improvement of up to 23% for multi-threaded applications and up to 27% for multiprogrammed workloads over that on statically chosen architectures, and up to 41% over the baseline SMP configuration. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1016/j.jpdc.2014.05.007 | Journal of Parallel and Distributed Computing |
Keywords | Field | DocType |
Reconfigurable architecture,MultiCore,ManyCore,Adaptive systems | Transistor count,Computer architecture,Architecture,Adaptive system,Program behavior,Computer science,Phase change,Parallel computing,Multicore architecture,Multi-core processor,Control reconfiguration | Journal |
Volume | Issue | ISSN |
74 | 11 | 0743-7315 |
Citations | PageRank | References |
2 | 0.43 | 36 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajesh Kumar Pal | 1 | 11 | 1.70 |
| Kolin Paul | 2 | 289 | 39.63 |
| Sanjiva Prasad | 3 | 301 | 40.04 |