Name
Abstract | ||
|---|---|---|
In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1142/S0218126615500395 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
Field programmable gate array,technology mapping,Boolean matching,decomposition,carry chain,cell configuration | Logic synthesis,Logic gate,Complex programmable logic device,Adder,Computer science,Programmable Array Logic,Programmable logic array,Field-programmable gate array,Electronic engineering,Programmable logic device | Journal |
Volume | Issue | ISSN |
24 | 3 | 0218-1266 |
Citations | PageRank | References |
1 | 0.39 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grace Zgheib | 1 | 21 | 6.40 |
| Iyad Ouaiss | 2 | 1 | 0.39 |