Name
Abstract | ||
|---|---|---|
Allowing cycles in a logic circuit can be advantageous, for example, by reducing the number of gates required to implement a given Boolean function, or a set of functions. However, a cyclic circuit may easily be ill behaved. For instance, it may have some output wire oscillation instead of reaching a steady state. Propositional three-valued logic has long been used in tests for good behavior of cy... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCAD.2014.2304176 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Delays,Wires,Lattices,Logic gates,Cognition,Integrated circuit modeling,Upper bound | Journal | 33 |
Issue | ISSN | Citations |
7 | 0278-0070 | 1 |
PageRank | References | Authors |
0.37 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Graeme Gange | 1 | 137 | 24.27 |
| Benjamin Horsfall | 2 | 1 | 0.70 |
| Lee Naish | 3 | 533 | 61.80 |
| Harald Søndergaard | 4 | 858 | 79.52 |