Name
Abstract | ||
|---|---|---|
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is presented. The simulator, named ASSESS, adopts fault models for SEUs affecting the configuration bits controlling both logic and routing resources that have been demonstrated to be much more accurate than classical fault models adopted by academic and industrial fault simulators currently available. ... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCAD.2014.2329419 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Circuit faults,Field programmable gate arrays,Routing,Integrated circuit modeling,Storage area networks,Logic gates | Journal | 33 |
Issue | ISSN | Citations |
9 | 0278-0070 | 6 |
PageRank | References | Authors |
0.46 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cinzia Bernardeschi | 1 | 226 | 31.87 |
| Luca Cassano | 2 | 62 | 11.36 |
| Andrea Domenici | 3 | 100 | 17.16 |
| Luca Sterpone | 4 | 233 | 41.54 |