Name
Title | ||
|---|---|---|
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs |
Abstract | ||
|---|---|---|
Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as n-type or p-type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing VDD and GND by complementary input signals. Synthesis results of ISCAS'85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCSI.2014.2333675 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
sequential circuits,semiconductor device models,configurable,silicon nanowire transistors,silicon nanowire,power consumption,size 22 nm,nanowires,dual-threshold-voltage design,vtr sequential benchmark circuits,schottky-barrier contacts,silicon,ambipolar,logic functions,field effect transistors,dual-threshold-voltage,si,iscas'85,elemental semiconductors,mosfet,finfet technology,logic gates,schottky barriers,dual-threshold-voltage configurable circuits | Logic gate,Pass transistor logic,NMOS logic,Controllability,Place and route,Electronic engineering,Electronic circuit,Transistor,Threshold voltage,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
61 | 10 | 1549-8328 |
Citations | PageRank | References |
10 | 0.85 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jian Zhang | 1 | 25 | 3.86 |
| Xifan Tang | 2 | 59 | 12.89 |
| Pierre-Emmanuel Gaillardon | 3 | 355 | 55.32 |
| Giovanni De Micheli | 4 | 10245 | 1018.13 |