Title
An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space.
Abstract
This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space ...
Year
DOI
Venue
2014
10.1109/TCSI.2014.2304656
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Delays,Dynamic range,Computer architecture,Redundancy,Power demand,Linearity,Error correction
Wide dynamic range,Electrical efficiency,Dynamic range,Computer science,Vernier scale,Electronic engineering,Redundancy (engineering),Time-to-digital converter,Offset (computer science),Least significant bit
Journal
Volume
Issue
ISSN
61
8
1549-8328
Citations 
PageRank 
References 
12
0.64
22
Authors
2
Name
Order
Citations
PageRank
Yeo Myung Kim1182.46
Tae Wook Kim28617.66