Name
Title | ||
|---|---|---|
Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference". |
Year | Venue | Field |
|---|---|---|
2014 | IEEE Trans. on Circuits and Systems | Phase-locked loop,Architecture,Low frequency,Spur,Low noise,Electronic engineering,Electrical engineering,Mathematics |
DocType | Volume | Issue |
Journal | 61-II | 8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiao Pu | 1 | 5 | 1.56 |
| Ajay Kumar | 2 | 24 | 6.99 |
| Krishnaswamy Nagaraj | 3 | 40 | 14.10 |