Paper Info
Title
Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design
Abstract
We propose a general model for array-based approximate arithmetic computing (AAAC) to guide the minimization of processing error. As part of this model, the Error Compensation Unit (ECU) is identified as a key building block for a wide range of AAAC circuits. We develop theoretical analysis geared towards addressing two critical design problems of the ECU, namely, determination of optimal error compensation values and identification of the optimal error compensation scheme. We demonstrate how this general AAAC model can be leveraged to derive practical design insights that lead to optimal tradeoffs between accuracy, energy dissipation and area overhead. To further minimize energy consumption, delay and area of AAAC circuits, we perform ECU design simplification by introducing logic don't cares. By applying this model and using a commercial 90 nm CMOS standard cell library, we propose an approximate 16 × 16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less energy and area compared with theoretically the most accurate fixed-width Booth multiplier. Furthermore, it reduces average error, max error and mean squared error by 11.11%, 28.11%, and 25.00%, respectively, when compared with the most accurate reported approximate Booth multiplier and outperforms the same design significantly by 19.10% for the energy-delay-mean squared error product. Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit. To further reduce error and cost by utilizing extra signatures and don't cares, we demonstrate a 16-bit fixed-width squarer that improves the energy-delay-max error product by 15.81%.
Year
DOI
Venue
2015
10.1109/TCSI.2015.2388839
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
logic circuits,cmos standard cell library,energy-delay-max error product,multiplier design,aaac circuits,squarer,energy-delay-mean squared error product,error compensation scheme,aaac,fixed-width booth multiplier,complimentary metal oxide semiconductor,squarer design,multiplier,logic design,size 90 nm,array-based approximate arithmetic computing,energy consumption,ecu,ecu design simplification,approximate arithmetic computing,error compensation unit,logic-do-not-cares,area reduction,error reduction,measurement,accuracy,computational modeling
Arithmetic,Mean squared error,Multiplier (economics),Electronic engineering,CMOS,Minification,Standard cell,Electronic circuit,Energy consumption,Mathematics,Booth's multiplication algorithm
Journal
Volume
Issue
ISSN
62
4
1549-8328
Citations 
PageRank 
References 
5
0.45
10
Authors
2
Name
Order
Citations
PageRank
Botang Shao150.45
Peng Li21912152.85