Name
Abstract | ||
|---|---|---|
This brief presents an improved timing scheme for a 4× interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end. This work enhances the ADC conversion rate up to 3.5 GS/s, for 4.1-mW power consumption. The peak spurious-free dynamic range and signal-to-noise-plu... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCSII.2014.2327340 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Clocks,Calibration,Frequency conversion,Synchronization,CMOS integrated circuits,Power demand | Dynamic range,Communication channel,Electronic engineering,CMOS,Cmos process,Bit time,Binary search algorithm,Successive approximation ADC,Mathematics,Power consumption | Journal |
Volume | Issue | ISSN |
61 | 7 | 1549-7747 |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Annachiara Spagnolo | 1 | 9 | 3.05 |
| Bob Verbruggen | 2 | 160 | 27.40 |
| Piet Wambacq | 3 | 529 | 96.10 |
| Stefano D'Amico | 4 | 129 | 27.42 |