Title
A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration.
Abstract
This paper presents a novel multi-standard digital low-IF receiver, which provides low-power low-complexity, flexible and robust performance for short distance communication applications. Over the various incoming data rates and carrier frequencies, the corresponding symbol timing is recovered by the Sigma Delta modulated frequency divider from fractional-N synthesizer, and the carrier frequency offset is calibrated by direct digital synthesizer generated intermediate frequency. The proposed digital receiver is fully integrated with 130 nm CMOS technology, occupying 0.83 mm(2) area with 4.5 mW. Through the verification in an FPGA, the measurement results show a great potential in flexible and cost oriented applications.
Year
DOI
Venue
2014
10.1109/TCSI.2014.2335391
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
Carrier frequency offset calibration, clock recovery, low complexity, low power, low-IF receiver, multi-standard
Frequency divider,Clock recovery,Intermediate frequency,Frequency offset,Carrier frequency offset,Electronic engineering,Frequency synthesizer,Low IF receiver,Direct digital synthesizer,Mathematics
Journal
Volume
Issue
ISSN
61-I
12
1549-8328
Citations 
PageRank 
References 
3
0.45
14
Authors
4
Name
Order
Citations
PageRank
Ye Zhang151.32
Jan Henning Mueller293.58
Bastian Mohr382.81
Stefan Heinen4154.67