Paper Info
Title
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
Abstract
This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV ( ~ 100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25 °C.
Year
DOI
Venue
2014
10.1109/TCSI.2014.2332267
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
power 22 muw,write-ability,multiple-bit errors,dapc,write-assist,data-aware,data-aware power-cutoff,interleaved storage,frequency 11.5 mhz,temperature 25 degc,ecc techniques,size 40 nm,sram chips,voltage 350 mv,low supply voltage,data-aware write-assist,error checking,cmos technology,subthreshold voltage,vddmin,sram cell,sram,soft error immunity,bit-interleaving,subthreshold sram,sram macro,radiation hardening (electronics),error correction
Soft error,Computer science,Voltage,CMOS,Chip,Electronic engineering,Static random-access memory,Subthreshold conduction,Threshold voltage,Interleaving
Journal
Volume
Issue
ISSN
61
9
1549-8328
Citations 
PageRank 
References 
18
0.77
13
Authors
7
Name
Order
Citations
PageRank
Yi-Wei Chiu1263.00
Yu-Hao Hu2181.11
Ming-Hsien Tu31049.89
Junkai Zhao4222.62
Yuan-Hua Chu5202.20
Shyh-Jye Jou6420275.67
Ching-Te Chuang746576.52