Name
Abstract | ||
|---|---|---|
Big data processing is becoming a standout part of data center computation. However, latest research has indicated that big data workloads cannot make full use of modern memory systems. We find that the dramatic inefficiency of the big data processing is from the enormous amount of cache misses and stalls of the depended memory accesses. In this paper, we introduce two optimizations to tackle these problems. The first one is the slice-and-merge strategy, which reduces the cache miss rate of the sort procedure. The second optimization is direct-memory-access, which reforms the data structure used in key/value storage. These optimizations are evaluated with both micro-benchmarks and the real-world benchmark HiBench. The results of our micro-benchmarks clearly demonstrate the effectiveness of our optimizations in terms of hardware event counts; and the additional results of HiBench show the 1.21X average speedup on the application-level. Both results illustrate that careful hardware/software co-design will improve the memory efficiency of big data processing. Our work has already been integrated into Intel distribution for Apache Hadoop. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/s11390-015-1502-9 | J. Comput. Sci. Technol. |
Keywords | Field | DocType |
big data, key/value pair, architecture awareness, performance measurement | Data structure,Cache,Computer science,Parallel computing,sort,Real-time computing,Software,Data center,Big data,Attribute–value pair,Speedup | Journal |
Volume | Issue | ISSN |
30 | 1 | 1860-4749 |
Citations | PageRank | References |
3 | 0.47 | 14 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong Yan | 1 | 17 | 6.40 |
| Xusen Yin | 2 | 5 | 1.19 |
| Cheng Lian | 3 | 312 | 9.99 |
| Xiang Zhong | 4 | 5 | 0.86 |
| Xin Zhou | 5 | 38 | 12.08 |
| Gansha Wu | 6 | 107 | 9.06 |