Paper Info
Title
Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network
Abstract
Three-dimensional (3D) integrated circuits, which use a vertically stacked design of 2D planar chips in a 3D arrangement using through-silicon-via (TSV) technology have been developed to minimise chip footprint, enable higher integration density, decrease power consumption and reduce fabrication cost. Floorplanning without considering power can increase the number of power TSVs and bumps needed to solve IR drop constraint in 3D power delivery network. In this study, the authors propose a methodology for minimising the power TSVs and bumps based on power-aware floorplanning using specific power patterns to solve IR drop constraint on the 3D power delivery network. The authors' methodology moves high power-consuming blocks to the dedicated pattern area which is able to minimise the number of power TSVs and bumps while solving the IR drop constraint. The simulation results show that the proposed method can reduce the total number of power TSVs and bumps by 13.7 and 12.2%, respectively, after power-aware floorplanning while solving the IR drop constraint.
Year
DOI
Venue
2014
10.1049/iet-cdt.2013.0118
IET Computers & Digital Techniques
Keywords
DocType
Volume
high power-consuming blocks,IR drop constraint,power-aware floorplanning-based power through-silicon-via technology,power consumption,three-dimensional power delivery network,three-dimensional integrated circuits,power TSVs,3D power delivery network,power patterns,3D integrated circuits,vertically stacked design,TSV technology,fabrication cost reduction,integrated circuit layout,chip footprint minimization,bump minimisation,2D planar chips,cost reduction
Journal
8
Issue
ISSN
Citations 
5
1751-8601
0
PageRank 
References 
Authors
0.34
10
3
Name
Order
Citations
PageRank
Cheoljon Jang100.68
Jaehwan Kim216626.08
Jong-Wha Chong312032.87