Name
Abstract | ||
|---|---|---|
A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1049/el.2014.4432 | Electronics Letters |
Keywords | Field | DocType |
decoding,field programmable gate arrays,FPGA,complexity successive cancellation,decoding algorithm,field programmable gate array,pipelined architecture,polar code,unrolled hardware polar decoder | Gigabit,Computer science,Parallel computing,Field-programmable gate array,Electronic engineering,Gate array,Polar code,Soft-decision decoder,Polar,Throughput,Decoding methods,Computer hardware | Journal |
Volume | Issue | ISSN |
51 | 10 | 0013-5194 |
Citations | PageRank | References |
14 | 0.71 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pascal Giard | 1 | 244 | 17.57 |
| Gabi Sarkis | 2 | 253 | 17.23 |
| Claude Thibeault | 3 | 14 | 0.71 |
| Warren J. Gross | 4 | 1106 | 113.38 |