Name
Abstract | ||
|---|---|---|
A novel digital network architecture, the sequential pipelined neurocomputer (SPIN), is proposed. The SPIN processor emulates neural networks, producing high performance with minimal hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/TAI.1991.167078 | San Jose, CA |
Keywords | Field | DocType |
neural nets,parallel processing,pipeline processing,systolic arrays,SPIN processor,digital network architecture,neural networks,neuromimetic neurocomputer architectures,recurrent systolic array,ring systolic array,sequential pipelined neurocomputer | Digital network,Spin-½,Computer science,Parallel computing,Tree (data structure),Recurrent neural network,Systolic array,Neuron structure,Emulation,Artificial neural network | Journal |
Volume | Issue | Citations |
2 | 1 | 2 |
PageRank | References | Authors |
0.46 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stamatis Vassiliadis | 1 | 2007 | 227.06 |
| Gerald G. Pechanek | 2 | 20 | 5.34 |
| José G. Delgado-frias | 3 | 91 | 29.03 |