Title
Loop scheduling with memory access reduction subject to register constraints for DSP applications
Abstract
AbstractMemory accesses introduce big-time overhead and power consumption because of the performance gap between processors and main memory. This paper describes and evaluates a technique, loop scheduling with memory access reduction LSMAR, that replaces hidden redundant load operations with register operations in loop kernels and performs partial scheduling for newly generated register operations subject to register constraints. By exploiting data dependence of memory access operations, the LSMAR technique can effectively reduce the number of memory accesses of loop kernels, thereby improving timing performance. The technique has been implemented into the Trimaran compiler and evaluated using a set of benchmarks from DSPstone and MiBench on the cycle-accurate simulator of the Trimaran infrastructure. The experimental results show that when the LSMAR technique is applied, the number of memory accesses can be reduced by 18.47% on average over the benchmarks when it is not applied. The measurements also indicate that the optimizations only lead to an average 1.41% increase in code size. With such small code size expansion, the technique is more suitable for embedded systems compared with prior work.Copyright ©2013 John Wiley & Sons, Ltd.
Year
DOI
Venue
2014
10.1002/spe.2186
Periodicals
Keywords
Field
DocType
DSP applications,loop optimization,memory optimization,instruction scheduling
Registered memory,Loop nest optimization,Interleaved memory,Uniform memory access,Physical address,Computer science,Parallel computing,Memory management,Overlay,Loop scheduling
Journal
Volume
Issue
ISSN
44
8
0038-0644
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
Yi Wang 0003100.34
zhiping jia246360.64
Renhai Chen31159.09
Meng Wang4808.46
Duo Liu521931.76
Zili Shao61618134.03