Name
Title | ||
|---|---|---|
Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation. |
Year | Venue | Field |
|---|---|---|
2014 | IEICE Electronic Express | Computer science,Modulation,Electronic engineering,Bitstream,Square root,Bit (horse) |
DocType | Volume | Issue |
Journal | 11 | 17 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong Liang | 1 | 16 | 4.19 |
| Zhigong Wang | 2 | 29 | 21.30 |
| Qiao Meng | 3 | 0 | 0.68 |
| Xiaodan Guo | 4 | 0 | 0.34 |
| Changchun Zhang | 5 | 24 | 8.42 |