Name
Abstract | ||
|---|---|---|
Simultaneous Multithreading (SMT) architectures are proposed to better explore on-chip parallelism, which capture the essence of performance improvement in modern processors. SMT overcomes the limits in a single thread by fetching and executing from multiple of them in a shared fashion. The long-latency operations, however, still cause inefficiency in SMT processors. When instructions have to wait for data from lower-level memory hierarchy, the dependent instructions cannot proceed, hence continue occupying the shared resources on the chip for an extended number of clock cycles. This introduces undesired inter-thread interference in SMT processors, which further leads to negative impacts on overall system throughput and average thread performance. In practice, instruction fetch policies take the responsibility of assigning thread priority at the fetch stage, in an effort to better distribute the shared resources among threads in the same core to cope with the long-latency operations and other runtime behavior from the thread for better performance. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1016/j.micpro.2014.10.001 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Instruction fetch policy,Simultaneous multithreading,Memory accessing resource,Computation resource,Thread management | Computer science,Inefficiency,Real-time computing,Throughput,Memory hierarchy,Parallel computing,Chip,Thread (computing),Fetch,Simultaneous multithreading,Operating system,Embedded system,Performance improvement | Journal |
Volume | Issue | ISSN |
39 | 1 | 0141-9331 |
Citations | PageRank | References |
0 | 0.34 | 24 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lichen Weng | 1 | 11 | 2.06 |
| Chen Liu | 2 | 82 | 16.75 |