Name
Title | ||
|---|---|---|
Efficient implementation of iterative multi-input–multi-output orthogonal frequency-division multiplexing receiver using minimum-mean-square error interference cancellation |
Abstract | ||
|---|---|---|
An efficient hardware implementation scheme is proposed for iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15-38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a Field Programmable Gate Array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1049/iet-com.2013.0694 | IET Communications |
Keywords | Field | DocType |
4-cordic qrd architecture,baseband turbo receiver,ldpc decoder,cordic cores,radiofrequency interference,cyclic codes,quasicyclic ldpc decoding,low-density parity-check decoder,min-sum algorithm,ofdm modulation,frequency-domain analysis,2d arrays,digital arithmetic,hardware implementation scheme,minimum mean square error interference cancellation,least mean squares methods,field programmable gate array,canonic-signed-digit method,one-dimensional arrays,mimo communication,systolic arrays,resource usages,mmse-ic detector,frequency domain least square channel estimation,interference suppression,coordinate rotation digital computer cores,receiver architecture,field programmable gate arrays,1d arrays,classic systolic array architectures,parity check codes,complex-valued matrices,iterative multiple-input multiple-output orthogonal frequency-division multiplexing receiver,decoding,iterative methods,channel estimation,mmse-ic equations,zadroff-chu sequence character,qr decomposition,frequency domain analysis | Low-density parity-check code,Single antenna interference cancellation,Minimum mean square error,Systolic array,Theoretical computer science,Real-time computing,Decoding methods,Computer hardware,Multiplexing,QR decomposition,Mathematics,Orthogonal frequency-division multiplexing | Journal |
Volume | Issue | ISSN |
8 | 7 | 1751-8628 |
Citations | PageRank | References |
1 | 0.37 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bing Han | 1 | 1 | 0.37 |
| Zengli Yang | 2 | 43 | 3.40 |
| Yahong Rosa Zheng | 3 | 885 | 76.15 |