Paper Info
Title
Energy-Efficient SRAM FPGA-Based Wireless Vision Sensor Node: SENTIOF-CAM
Abstract
Many wireless vision sensor networks (WVSNs) applications are characterized to have a low duty cycling. An individual wireless vision sensor node (VSN) in WVSN is required to complete the tasks as quickly as possible. The execution of the tasks can be speeded up by exploiting the inherited parallelism in the tasks by using a hardware platform such as field-programmable gate array (FPGA). Traditionally, SRAM FPGAs are considered to be inefficient for duty cycled applications. This paper presents a low-complexity, energy-efficient, and reconfigurable VSN architecture based on SRAM FPGA using a design matrix, which includes tasks' partitioning, a low-complexity background subtraction, bilevel coding, and duty cycling. The proposed VSN, referred to as SENTIOF-CAM, has been implemented on a prototype board and energy values of different states are measured for three real applications. The comparison results with existing solutions show that the proposed architecture with SRAM FPGA can achieve energy reduction of up to a factor of 69 as compared with software VSN solutions and approximately similar energy values to that for the FLASH FPGA-based VSN solutions. The lifetime based on measured energy values shows that, for a sample period of 5 min, a 3.2-years lifetime can be achieved with a battery of 37.44-kJ energy. In addition, the proposed solution offers a generic architecture with a smaller design complexity on a hardware reconfigurable platform and offers easy adaptation for a number of applications.
Year
DOI
Venue
2014
10.1109/TCSVT.2014.2330660
Circuits and Systems for Video Technology, IEEE Transactions  
Keywords
Field
DocType
SRAM chips,energy conservation,field programmable gate arrays,image sensors,low-power electronics,wireless sensor networks,SENTIOF-CAM,bilevel coding,design matrix,duty cycling,energy efficient SRAM FPGA-based wireless vision sensor node,field programmable gate array,low complexity background subtraction,task partitioning,Architecture,SRAM fieldprogrammable gate array (FPGA),image coding,wireless vision sensor networks (WVSNs),wireless vision sensor node (VSN)
Background subtraction,Key distribution in wireless sensor networks,Wireless,Efficient energy use,Computer science,Field-programmable gate array,Static random-access memory,Gate array,Wireless sensor network,Embedded system
Journal
Volume
Issue
ISSN
24
12
1051-8215
Citations 
PageRank 
References 
4
0.57
11
Authors
8
Name
Order
Citations
PageRank
Muhammad Imran Shahzad1366.22
Khurram Shahzad271.03
Naeem Ahmad34712.24
Mattias O'nils412126.67
Najeem Lawal57213.94
B Oelmann67721.78
Muhammad Ali Imran72920278.27
O'Nils, M.881.34