Name
Abstract | ||
|---|---|---|
The image processing nowadays is a field in development, many image filtering algorithms are tested every day; however, the main hurdles to overcome are the difficulty of implementation or the time response in a general purpose processors. When the amount of data is too big, a specific hardware accelerator is required because a software implementation or a generic processor is not fast enough to respond in real time. In this paper optimal hardware implementation is proposed for extracting edges and noise reduction of an image in real time. Furthermore, the hardware configuration is flexible with the ability to select between power and area optimization or speed and performance. The results of algorithms implementation are reported. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1007/978-3-319-12568-8_10 | PROGRESS IN PATTERN RECOGNITION IMAGE ANALYSIS, COMPUTER VISION, AND APPLICATIONS, CIARP 2014 |
Keywords | Field | DocType |
Image filtering, image convolution, edge detecting, noise reduction, field-programmable gate array, FPGA, hardware accelerator, hardware design, high performance computing, image kernel, Verilog | Noise reduction,Supercomputer,Computer science,Field-programmable gate array,Image processing,Filter (signal processing),Real-time computing,Hardware acceleration,Verilog,Kernel (image processing) | Conference |
Volume | ISSN | Citations |
8827 | 0302-9743 | 1 |
PageRank | References | Authors |
0.35 | 7 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Susana Ortega-Cisneros | 1 | 25 | 6.85 |
| Miguel A. Carrazco-Díaz | 2 | 1 | 0.69 |
| Adrian Pedroza de-la-Crúz | 3 | 1 | 0.69 |
| Juan José Raygoza-Panduro | 4 | 17 | 3.75 |
| Federico Sandoval-Ibarra | 5 | 1 | 1.03 |
| Jorge Rivera | 6 | 78 | 9.24 |